A Novel Dimension Reduction Technique for 3d Capacitance Extraction of Vlsi Interconnects
نویسندگان
چکیده
abstract In this paper, a new method named Dimension Reduction Technique (DRT) is presented for capacitance extraction of 3D multilayer and multiconductor interconnects. In this technique, a complex 3D problem is decomposed to a series of simpler 2D problems. Therefore, it results in dramatical savings in computing time and memory usage. Compared to FASTCAP, a eld solver based on BEM with multipole acceleration and developed from MITTNW92], DRT is generally an order of magnitude faster with signiicantly less memory usage. Based on this technique, accurate close-form formulae or data base can be generated eeciently for calculating the capacitances of some typical 3D structures of VLSI interconnect.
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